Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras

Course Lectures

• Mod-01 Lec-01 Introduction to Digital VLSI Design Flow

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-01 Lec-02 High Level Design Representation

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-01 Lec-03 Transformations for High Level Synthesis

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-02 Lec-01 Introduction to HLS: Scheduling, Allocation and Binding Problem

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-02 Lec-02 Scheduling Algorithms-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-02 Lec-03 Scheduling Algorithms-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-02 Lec-04 Binding and Allocation Algorithms

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-03 Lec-01 Two level Boolean Logic Synthesis-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-03 Lec-02 Two level Boolean Logic Synthesis-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-03 Lec-03 Two level Boolean Logic Synthesis-3

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-03 Lec-04 Heuristic Minimization of Two-Level Circuits

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-03 Lec-05 Finite State Machine Synthesis

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-03 Lec-06 Multilevel Implementation

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-04 Lec-01 Introduction to formal methods for design verification

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-04 Lec-02 Temporal Logic: Introduction and Basic Operators

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-04 Lec-03 Syntax and Semantics of CTL

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-04 Lec-04 Syntax and Semantics of CTL -- Continued

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-04 Lec-05 Equivalence between CTL Formulas

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-05 Lec-01 Introduction to Model Checking

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-05 Lec-02 Model Checking Algorithms I

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-05 Lec-03 Model Checking Algorithms II

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-05 Lec-04 Model Checking with Fairness

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-06 Lec-01 Binary Decision Diagram: Introduction and construction

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-06 Lec-02 Ordered Binary Decision Diagram

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-06 Lec-03 Operation on Ordered Binary Decision Diagram

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-06 Lec-04 Ordered Binary Decision Diagram for State Transition Systems

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-06 Lec-05 Symbolic Model Checking

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-07 Lec-01 Introduction to Digital VLSI Testing

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-07 Lec-02 Functional and Structural Testing

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-07 Lec-03 Fault Equivalence

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-08 Lec-01 Fault Simulation-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-08 Lec-02 Fault Simulation-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-08 Lec-03 Fault Simulation-3

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-08 Lec-04 Testability Measures (SCOAP)

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

  Playing
• Mod-09 Lec-02 D-Algorithm-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-09 Lec-03 D-Algorithm-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-10 Lec-01 ATPG for Synchronous Sequential Circuits

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-10 Lec-02 Scan Chain based Sequential Circuit Testing-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-10 Lec-03 Scan Chain based Sequential Circuit Testing-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-11 Lec-01 Built in Self Test-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-11 Lec-02 Built in Self Test-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-11 Lec-03 Memory Testing-1

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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• Mod-11 Lec-04 Memory Testing-2

  Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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